1. Field of Invention
This invention relates to a switching power supply which is provided with a primary output circuit and a secondary output circuit and which is capable of outputting a plurality of D.C. voltages; wherein a D.C. output voltage of a set value is obtained by controlling the widths of pulses obtained from a square waveform voltage supplied to the secondary output circuit; and more particularly, to an improvement of the secondary output circuit.
2. Description of the Prior Art
FIG. 1 shows an example of a conventional multi-output switching power supply provided with a primary output circuit and a secondary output circuit. FIGS. 2(1)-2(3) show waveforms of signals at different parts of the FIG. 1 circuit.
The primary output circuit 1 is an output circuit for supplying a voltage V1 which serves as the basis for a signal S1 for controling a main switch Q1 on the primary side of transformer T1.
Control circuit 3 outputs a pulse width signal which renders output voltage V1 of primary output circuit 1 equal to a set voltage (not shown), thus controlling the duty ratio of switch Q1, that is the ON rate of Q1 per unit time. As a result, a voltage Vw3 whose duty ratio has been changed is induced in secondary winding W3. Voltage Vw3 is rectified and smoothed, and its duty ratio stabilized at points where primary output voltage V1 of the circuit and the set voltage are uniform. Primary output circuit 1 comprises a secondaary winding W3, a diode D1, for rectifying the voltage induced in secondary winding W3, a smoothing circuit comprising a choke coil L1 and a capacitor C1, and a diode D2 for discharging the energy stored in choke coil L1. The value of output voltage V1 of primary output circuit 1 is isolated by a photocoupler 2, and is fed to the primary side of transformer T1.
Secondary output circuit 10 is a circuit connected to secondary winding W2 of transformer 1, which is wound separately from winding W3, and obtains a DC. voltage V2 from voltage induced in winding W2.
The duty ratio of the voltage Vo of winding W2 changes according to input voltage Vin or load current Iout of primary output circuit 1. Incidently, whenever we use the word "duty ratio" it means the voltage ratio which results in a device's ON rate per unit time. Going back to the duty ratio of voltage Vo if countermeasures are not taken, DC output voltage V2 of secondary output circuit 10 will fluctuate. Accordingly, secondary output circuit 10 is generally provided with means for stabilizing secondary output voltage V2. In FIG. 1, the stabilizing means comprises a synchronizing signal generator 6, a control circuit 5, a drive transformer T2, a drive circuit 4, and an FET switch Q2. "FET" means field effect transistor, as used herein.
In FIG. 1, induction voltage Vo (also see FIG. 2(1)) of winding W2 is rectified by diode D3 and supplied to switch Q2. The ON/OFF functions of FET Q2 are controlled by drive circuit 4. The amount of voltage passing through FET Q2 is smoothed by choke coil L2 and capacitor C2, and such voltage then becomes the secondary output voltage V2 which has reduced ripples. Diode D4 discharges the energy soted in choke coil L2 during the OFF periods of FET Q2.
The stability of voltage V2 is achieved by appropriately chopping, in FET Q2, the pulse width (see FIG. 2(1)) of induction voltage Vo from winding W2, and supplying the resulting signal to the smoothing circuit comprising choke coil L2 and capacitor C2.
The control of FET Q2 is achieved as follows, with reference being made to FIGS. 2(1)-2(3). An FET Q3, connected to control circuit 5, carries out switching operations, while a transformer T2 carries out level changes of output Va of control circuit 5.
The circuit of FIG. 1 operates as follows. A DC voltage Vin is generated at both ends of capacitor C3, and the ON/OFF functions of switching element Q1 are controlled by control circuit 3. Accordingly, a voltage is intermittently supplied to primary winding W1, with the result that an induction voltage is generated in windings W2 and W3.
Primary output voltage V1, obtained from primary output circuit 1, is fed back to the primary side of transformer T1 via the photocoupler 2. Then, a pulse width modulation signal S1 is produced in control circuit 3 for conforming primary output voltage V1 to a set voltage (not shown), and the duty ratio of the primary siwtch FET 01 is controlled based on signal S1.
The duty ratio of voltage Vo, induced in the secondary winding W2, fluctuates according to input voltage Vin or the load current Iout of primary output circuit 1. This is because, when input voltage Vin decreases, in order to uniformly maintain primary output voltage V1, the duty ratio of primary switch FET Q1 is increased. In other words, by increasing the rate at which FET Q1 is switched ON, due to the reduction of voltage Vin, the amount of current supplied to winding W3 is compensated for.
Also, if load current Iout of primary output circuit 1 increases, in order to maintain uniformity of voltage V1, the duty ratio of FET Q1 also is increased.
Consequently, the duty ratio of the induction voltage from winding W2, which is wound about the same core as winding W3, is also increased.
Where the duty ratio of the induction voltage from winding W2 fluctuates, if countermeasures are not taken, output voltage V2 will also fluctuate. Since fluctuation of output voltage V2 is a major problem, the circuit of FIG. 1 performs a control operation which makes the voltage V2 uniform.
Such control operation is as follows. As previously described, input voltage Vo supplied to secondary output circuit 10 has the shape of waveform shown in FIG. 2(1). Input voltage Vo is fed to synchronizing signal generator 6 which outputs a synchronizing signal Vc (see FIG. 2(3)) which is in a modified sawtooth waveform shape, only during time period Tp when the input voltage Vo (see FIG. 2(1)) is at a high level. Synchronizing signal Vc is synchronized to the switching waveform of the primary side of transformer T1. Synchronizing signal generator 6 detects the ON (i.e. high) state of induction voltage Vo (see FIG. 2(1)) of winding W2 and produces the above described modified sawtooth waveform. Control circuit 5 receives both synchronizing signal Vc, having the waveform of FIG. 2(3), and secondary output voltage V2, and produces a references signal VK (see FIG. 2(3)).
When secondary output voltage V2 of secondary output circuit 10 is higher than a set voltage (not shown), reference voltage VK (see FIG. 2(3)) produced by control circuit 5 increases. Control circuit 5 outputs a high level signal Va during the period when the value of synchronizing signal Vc shown in FIG. 2(3) is higher than the reference voltage VK produced within control circuit 5. Output signal Va is applied to and drives FET Q3 ON/OFF. The voltage on the primary side of transformer T2 is boosted and this boosted voltage is supplied to drive circuit 4.
More specifically, when secondary output voltage V2 is higher than a set voltage, reference voltage VK, shown in FIG. 2(3) increases. Consequently, the period when the value of synchronizing signal Vc is higher than the reference signal VK, i.e., the period when the FET Q2 is ON, is reduced. As a result, since the amount of voltage supplied to the smoothing circuit, comprising choke coil L2 and capacitor C2, also decreases, the value of voltage V2 decreases and approaches the set voltage value.
Conversely, when voltage V2 is lower than the set voltage, reference voltage VK decreases, and the operation described above occurs in reverse, i.e., the ON period of FET Q2 is increased, and since the amout of voltage supplied to smoothing circuit increases, voltage V2 also increases, and approaches the set voltage.